The present invention relates to a method for forming a capacitor of a semiconductor device, and more particularly, to a method for forming a capacitor of a semiconductor device which can prevent a storage node from leaning.
In a memory device such as a DRAM (dynamic random access memory), the area designated to be occupied by a capacitor for storing data decreases. As such, various alternatives for securing a high capacitance have been proposed in the art. Also, an MIM (metal-insulator-metal) capacitor has recently come to the forefront. In the MIM capacitor a metal having a large work function is adopted as the material for the electrodes in order to provide a high-performance memory device.
In general, in order to secure high capacitance, a dielectric layer having a high dielectric constant is used, the surface area of the electrode is increased, and the distance between electrodes is decreased. However, limitations exist when decreasing the distance between electrodes (the thickness of a dielectric layer). Therefore, high capacitance is typically secured by using a dielectric layer having a high dielectric constant or increasing the surface area of an electrode.
In a method for increasing the surface area of an electrode, a storage node can be formed as a concave type storage node or a cylinder type storage node. In recent designs, the cylinder type storage node has been preferred over the concave type storage node. The reason behind this resides in that limitations exist when increasing the height of a capacitor as the area of the capacitor decreases due to the decrease in the size of a cell; as such, it is difficult to sufficiently secure the surface area of an electrode in a capacitor having a concave type storage node. Therefore, the cylinder type capacitor has been preferred to the concave type capacitor, because the concave type storage node only uses the inside area of a storage node, while the cylinder type storage node uses both the inside and outside areas of a storage node.
Hereinbelow, a conventional method for forming a cylinder type MIM capacitor will be schematically described with reference to FIGS. 1A and 1B.
Referring to FIG. 1A, a semiconductor substrate 110 is first prepared. The semiconductor substrate 110 is divided into a cell region and a peripheral region, each having predeposition layers. An interlayer dielectric 120 is formed on the semiconductor substrate 110. Storage node contacts 130 are formed in specified portions of the interlayer dielectric 120 in the cell region. A sacrificial insulation layer 150 having a substantial thickness is deposited on the interlayer dielectric 120 including the storage node contacts 130. The sacrificial insulation layer 150 is then etched to define holes that both expose the storage node contacts 130 and delimit areas in which storage nodes are to be formed. A metal layer for storage nodes is deposited on the surfaces of the holes and on the sacrificial insulation layer 150, and then a portion of the metal layer deposited on the sacrificial insulation layer 150 is removed to form storage nodes 170.
Referring to FIG. 1B, the sacrificial insulation layer 150 is removed through wet etching using BOE (buffered oxide etchant), thus completing the formation of the cylinder type storage nodes 170 in the cell region. A rinsing process using DI (deionized) water is implemented on the resultant semiconductor substrate 110 formed with the cylinder type storage nodes 170 so as to remove any remaining foreign substance (for example an etching solution). A drying process is then implemented to remove the DI water.
Thereupon, while not shown in the drawings, both a dielectric layer and a metal layer for plate nodes is formed on the cylinder type storage nodes 170. The metal layer for plate nodes and the dielectric layer are then etched, and plate nodes are formed, whereby cylinder type capacitors composed of the storage nodes 170, the dielectric layer, and the plate nodes are formed.
In the conventional art as described above, when forming the cylinder type storage nodes 170, the sacrificial insulation layer 150 is removed by implementing the wet etching process and the rinsing process. When the wet etching process and the rinsing process are conducted, if any remnants remaining on the surface of the semiconductor substrate 110 are not displaced by IPA (isopropyl alcohol), a water drop may be present between adjoining storage nodes; and due to the water drop, a water mark may be produced in the subsequent drying process for removing the remnants of the wet etching and drying process.
In this situation, as shown in FIG. 2, the presence of the water mark generates surface tension causing a bridge to be formed between the adjoining storage nodes 170, as a result of which leaning of the storage nodes 170 is caused. If this leaning of the storage nodes 170 occurs at one place in each die of a DRAM device, since it is impossible to repair the leaning, a detrimental influence is exerted on the manufacturing yield of a semiconductor device.